Foreword: Beyond3D is gradually catching up with itself, and this is another one in a line of late articles! This time however, it's not all down to the hands of B3D.
During his visit to ECTS 2000, Kristof did the rounds of the 3D vendors and was handed another reference KYRO board for review by Imagination Technologies. What made this one different from the one used in Kristof's KYRO preview was that it was a 32MB model, much closer to the retail versions released by Videologic. Soon after, Kristof was getting ready to make the switch to being a 3dfx employee, and so the KYRO went on more European travel back to it's native county in England and into my hands.
Unfortunately the KYRO board suffered configuration
conflicts with my SCSI card and the review got sidelined because of
this; obviously there were also our server issues etc., etc.! Now though,
Imagination Technologies has endeavoured to send me a 'proper' retail
KYRO Vivid!, a BIOS update that fixes SCSI conflicts, and we even have
some newer drivers. Finally we are all set for a proper review of Imagination
Technologies Videologic Vivid! 32MB KYRO board!
Persistently late since the PCX2, and their concentration on Sega's Dreamcast console, you'd be forgiven for thinking that Videologic has a 'take it, or leave it' attitude to the PC graphics card market. The announcement of PowerVR Series 3 A.K.A. KYRO last year and the interminable wait for it to actually appear on the shelves did little to sway that impression.
Now, however, Videologic's Vivid!, utilising the KYRO graphics core, is readily available. With an asking price of just Â£99 (GBP) this is placed firmly in the entry level graphics card price range, but while we were waiting for KYRO, competitors have entered into this market with impressive chips such as NVIDIA's GeForce2 MX, the as yet unseen ATI Radeon VE, and the slightly more expensive Radeon SDR. It remains to be seen if KYRO's trickery makes it a worthy contender.
For those that aren't familiar with the PowerVR technology employed
by KYRO (as well as the previous PowerVR chips preceding it - Neon250,
PCX2, PCX1 and the Sega Dreamcast 3D chip), it utilises a method commonly
know as 'tiling'. Tiling refers to a small on- chip cache capable of
storing a sample of the frame buffer, usually 32x16 pixels in size (hence
'Tile'); this in itself doesn't sound fantastic (although it offers
a number of other benefits, as explored later on) because the important
part occurs before we even get to that point.
Traditional 3D architectures, such as any of the Voodoo's or NVIDIA's cards from Riva to GeForce series, etc. are kind of 'unintelligent' in how they render. When they render a polygon they know what depth (Z value) it has within the scene, but they have no knowledge of the depth of the polygons still to come; this means that polygons still to come may be in front of those that already passed to the frame buffer, and will overwrite the values already calculated. The process of overwriting values that have already been calculated is known as 'overdraw'. The quantity of overdraw within a scene is least 40%, however todays more complex games are said to have an overdraw of about 3.5 times, meaning that a traditional renderer may be calculating and drawing 3.5 times more pixels (and wasting the associated bandwidth doing these operations) than they "need" to.
The 'Tiling' element of PowerVR's architecture is actually only a means of making the scene more manageable. The actual full name for PowerVR's rendering architecture is 'Tile Based Deferred Rendering'; Deferred Rendering being the important part. Deferred Rendering enables PowerVR to cut out overdraw entirely, by a process of 'polygon binning' and 'Per Pixel Sorting'; only what will ultimately be seen on-screen will be rendered.
A traditional renderer will render whatever polygon is sent to it by the CPU/T&L unit regardless of where it occurs within the scene; PowerVR 'stores' the polygon scene in memory, as it is being sent to it, and divides the scene into 'tiles' -- the same size as the tile cache on chip. Once the entire geometry has been sent for a full frame, the chip will systematically 'sort' the geometry data in the tiles, to remove any information that is hidden, or overdrawn, and render only the scene data that will actually be visible. During this process the chip will render one tile, whilst already 'sorting' the next that is due to be rendered.
One potential disadvantage to this process is that it results in one frame of latency - the entire scene data is buffered up before the rendering of that scene begins. Also the geometry data has to be stored in the cards local memory for the Binning and Sorting, hence some of the 32MB available on the card will be used up for this. However, the obvious upside is that it only ever draws the data that is going to be seen onscreen.
Personally I'm of the opinion that this type 'tiling' architecture, or variants of it, will be seen more often in the future. ATi are known to have a patent relating to tiling, 3dfx (before they died) bought out GigaPixel, another company formed mainly from ex-SGI staff who produced working tiling architectures; this, of course, is now owned by NVIDIA and it remains to be seen if they will utilise it as they have talked down the concept of tilers before. However, right now Videologic already have PowerVR and they have in excess of 6 years of practice doing it!