Matrox Parhelia Chip Details
| Main Chip Details | |
|---|---|
| Manufacturer | Matrox |
| Process | 150nm |
| Foundry | UMC |
| Transistor Count | 80M |
| Die Size | 0mm² mm x mm |
| Chip Package | |
| Memory Bus | |
|---|---|
| Bus Width | 256-bit |
| Memory Channels | 1 x 256-bit |
| Memory Type Support | DDR |
| Geometry Pipeline | |
|---|---|
| Geometry Processing | VS2.0 |
| Processor Configuration | 4 Vertex Shader |
| Rasteriser | |
|---|---|
| Basic Pipeline Config |
16 / 4 / 4 Textures / Pixels / Z |
| Textures Per Pass | 4 |
| Basis Filtering | Bilinear |
| Texture Filtering Methods | |
| Texture Compression | DXTC (1-5), S3TC |
| Fragment Processing | PS1.3 |
| Fragment Processing Precision | |
| Fragment Processors | |
| FSAA | |
|---|---|
| FSAA Support | Fragment, Super-Sampling |
| ROP Subsamples | 16 |
| Subsampling Method | 16X Ordered Grid Fragement AA, 4X Ordered Grid Super-Sampling |
| Further Details | |
|---|---|
| API Compliance | DX8.0 |
| System Interconnect | AGP4X |
| Display Pipeline | Dual 10-bit, 400MHz DACs plus 230MHz DAC |
| Multi GPU Support | |