PowerVR/ST STG4500 Chip Details
| Main Chip Details | |
|---|---|
| Manufacturer | PowerVR/ST |
| Process | 180nm |
| Foundry | TSMC |
| Transistor Count | 15M |
| Die Size | 0mm² mm x mm |
| Chip Package | Wirebond |
| Memory Bus | |
|---|---|
| Bus Width | 128-bit |
| Memory Channels | 1 x 128-bit |
| Memory Type Support | SDR |
| Geometry Pipeline | |
|---|---|
| Geometry Processing | |
| Processor Configuration | |
| Rasteriser | |
|---|---|
| Basic Pipeline Config |
2 / 2 / 2 Textures / Pixels / Z |
| Textures Per Pass | 8 |
| Basis Filtering | Bilinear |
| Texture Filtering Methods | Bilinear, Trilinear, Box Filtered Trilinear (Compr |
| Texture Compression | DXT1, S3TC |
| Fragment Processing | Dot3, EMBM |
| Fragment Processing Precision | 8-bit |
| Fragment Processors | |
| FSAA | |
|---|---|
| FSAA Support | Super-Sampling |
| ROP Subsamples | 1 |
| Subsampling Method | Ordered Grid |
| Further Details | |
|---|---|
| API Compliance | DX6.0 |
| System Interconnect | AGP2X |
| Display Pipeline | |
| Multi GPU Support | |