S3 Savage 2000 Chip Details
| Main Chip Details |
| Manufacturer |
S3 |
| Process |
180nm |
| Foundry |
|
| Transistor Count |
M |
| Die Size |
0mm²
mm x mm |
| Chip Package |
Wirebond |
| Memory Bus |
| Bus Width |
128-bit |
| Memory Channels |
1 x 128-bit |
| Memory Type Support |
SDR |
| Geometry Pipeline |
| Geometry Processing |
T&L |
| Processor Configuration |
|
| Rasteriser |
| Basic Pipeline Config |
4 / 2 / 2
Textures / Pixels / Z
|
| Textures Per Pass |
2 |
| Basis Filtering |
Bilinear |
| Texture Filtering Methods |
Bilinear, Trilinear (Box Filtering), Anisotropic |
| Texture Compression |
S3TC / DXTC |
| Fragment Processing |
Dot3 |
| Fragment Processing Precision |
32-bit |
| Fragment Processors |
|
| FSAA |
| FSAA Support |
|
| ROP Subsamples |
|
| Subsampling Method |
|
| Further Details |
| API Compliance |
DX6.1 |
| System Interconnect |
AGP4X |
| Display Pipeline |
350MHz RAMDAC |
| Multi GPU Support |
|
Notes
T&L Implementation was somewhat "buggy" - only ever implemented in Beta drivers. Chip is based on a hybrid 180/220nm node, with the transistors rated at "180nm" and the rest of the chips at 220nm.
