GT200: Thoughts on positioning and the NVIO Display Pipe

It's easy enough to be blasé as the writer talking about the architecture. Here's hoping the differences present don't add up to conclusions of “it's just a wider G80” in the technical press. It's a bit more than that, when surfaces are scratched (and sampled and filtered, since we're talking about graphics).

The raw numbers do tell a tale, though, and it's no small piece of silicon even in 55nm form as a 'GT200b'. In fact, it's easily the biggest single piece of silicon ever sold to the general PC-buying populace, and we're confident it'll hold that crown until well into 2009. When writing about GT200 I've found my mind wandering to that horribly cheesy analogy that everyone loves to read about from the linguistically-challenged technical writer. What do I compare it to that everyone will recognise, that does it justice? I can't help but imagine the Cloverfield monster wearing a dainty pair of pink ballerina shoes, as it destroys everything in the run to the end game. Elegant brawn, or something like that. You know what I mean. That also means I get to wonder out loud and ask if ATI are ready to execute the Hammer Down protocol.

It'll need to if it wants to conquer a product stack that'll see NVIDIA make use of cheap G92 and G92b (55nm) based products underneath the GT200-based models it's introducing today. That leads us on nicely to talking about how NVIDIA can scale GT200 in order to have it drive multiple products scaled not just in clock, but in enabled unit count.

GT200 is able to be scaled in terms of active cluster count and the number of active ROP partitions, at a basic level. At a more advanced level, the FP64 ALU is freely removed, and we fully assume that to be the case for lower-end derivatives. For this chip though, it follows the same redundancy and product scaling model that we famously saw with G80 and then G92. So initially, we'll see a product based on the full configuration of 10 clusters and 8 ROP partitions, with the full 512-bit external memory bus that brings. Along with that there'll be an 8 cluster model with 448-bit memory interface (so a single ROP partition disabled there). Nothing exciting then, and what one would reasonably expect given the past history of chips with the same basic architecture.

Display Pipe

We've tacked it on to the back end of the architecture discussion, but it's worth mentioning because of how it's manifest in hardware. So as far as the display pipe goes, you've got the same 10bpc support as G80, and it's via NVIO (a new revision) again this time. The video engine is almost a direct cut and paste from G84, G92 et al, so we get to call it VP2 and grumble under our breath about the overall state of PC HD video in the wake of HD DVD losing out to BluRay. It's based on Tensilica IP (just like AMD's UVD), NVIDIA using the company's area-efficient DSP cores to create the guts of the video decode hardware, with the shader core used to improve video quality rather than assist in the decode process. The chip supports a full range of analogue and digital display outputs, including HDMI with HDCP protection, as you'd expect from a graphics product in the middle of 2008.

To portend to DisplayPort port support.... it's possible, but that's up to the board vendor and whether they want to use an external transmitter. Portunately they can.