NVIDIA confirms Next-Gen close to 1TFlop in 4Q07

Wednesday 23rd May 2007, 12:12:00 PM, written by Arun

In recent analyst conferences that were publicly webcast on NVIDIA's website, Michael Hara (VP of Investor Relations) has claimed that their next-generation chip, also known as G92 in the rumour mill, will deliver close to one teraflop of performance. In a separate answer to an analyst's question, he also noted that they have no intention from diverging from the cycle they have adopted with the G80, which is to have the high-end part ready at the end of the year and release the lower-end derivatives in the spring.

Assuming that NVIDIA manages to hit these aggressive release schedules, it implies that the chip will compete with any potential R6xx refresh at the beginning of its lifetime, but also eventually with R700 as it seems unlikely NVIDIA will refresh again before the second half of 2008, unless they go for an optical shrink from 65nm to 55nm. It also remains to be seen how aggressive ATI will be on the process front this time around.

There also were a number of other highlights during the conference, including a major emphasis on GPGPU (aka 'GPU Computing') and a short mention of Intel's upcoming GPU efforts through their Larrabee project. Micahel Hara seemed far from certain about Intel's exact strategy there, although he did mention that it was possible Intel was more interested in the GPGPU market than the gaming one. This is something we have already said in the past.

And finally, he mentioned that although he does not believe R600 will have any impact on their G80 sales, RV610 and RV630 are much more competitive parts that are likely to gain traction in the marketplace. He argued that he was not convinced 65nm gave AMD a real advantage in terms of costs because of the yield curve, and seemed confident that their own 65nm mainstream parts will be superior. We can't help but wonder how much that matters when you release them 9 months later, though? It will also be interesting to see who's first to 55nm, and how good of a half-node it will be.
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nvidia ± g92, r650, rv670, r700

Latest Thread Comments (146 total)
Posted by Jawed on Thursday, 07-Jun-07 13:28:38 UTC
Quoting dnavas
If quad X always goes to TMUx, then a predication mask that always masks (say) quad 2, will leave TMU2 without any work to do.
Ah, OK, that's the kind of thing synthetics are for. Actually, that'd prolly make a really good synthetic for testing the performance of R600 texturing. Similar to dynamic branching tests that only use rectangular areas of coherence. Which reminds me of a similar possibility with the way textures are defined and then fetched. It's possible to use a stride that will hit only one memory channel.
I'm not sure how a local TMU uses the ring at all -- local ALUs talk to local TMUs, I wouldn't expect that to be over the ring.
No, but some of the texels could be in a foreign TMU's L2 already. Presuming that L2 is distributed - which I'm assuming is the case for the time being...
As it is, ALUs are always talking to remote TMUs (how remote depends on which quad). Have I misunderstood something? [that's a stupid question ;)] What have I misunderstood?
No, I don't think you misunderstood anything. I might draw a diagram of how I think it all hangs together at some point... Ooh, hang on, there's this from Watch Impress Image: http://pc.watch.impress.co.jp/docs/2007/0515/kaigai03.jpg I wish AMD would just post the complete set of slides. Anyway, that doesn't show the ring bus at all, so I prolly should still have a go at a more detailed diagram. Jawed

Posted by mhouston on Thursday, 07-Jun-07 14:28:43 UTC
Eric Demers gave a talk about the R6XX processors at Stanford's CS448 and AMD actually let us post the slides. http://graphics.stanford.edu/cs448-07-spring/. The talk was not a completely deep technical dive as it was in some ways designed to inspire students aiming to become architects and talk about why some things were done.

Posted by Geo on Thursday, 07-Jun-07 14:44:06 UTC
Quoting Jawed

I wish AMD would just post the complete set of slides.

Anyway, that doesn't show the ring bus at all, so I prolly should still have a go at a more detailed diagram.

We have Eric's architecture deep-dive from Tunis. We also have a long list of interview questions into Eric. Hopefully these things get published together. . .

Posted by Jawed on Thursday, 07-Jun-07 14:45:22 UTC
Thanks Mike, that's great. That'll keep me busy for a while! There's an admittedly vague die picture for those who like pretty pix. Jawed

Posted by 3dilettante on Thursday, 07-Jun-07 15:00:27 UTC
I'm kind of confused as to why GPU makers insist on die shots where the innards are obscured by the pinout. Don't they use the same kind of packaging scheme?

CPU makers seem to have no issue with showing higher-res and more clear die shots. They sometimes even go out of their way to draw borders around functional units.

Posted by Jawed on Thursday, 07-Jun-07 15:04:49 UTC
Xenos and R520 die shots are comparatively clear... Jawed

Posted by 3dilettante on Thursday, 07-Jun-07 15:09:23 UTC
I haven't seen any hi-res die shots of those cores. I haven't looked too hard for R520 shots, but I don't recall seeing a good pic of Xenos either.

Is there a presentation or article I missed?

Posted by Jawed on Thursday, 07-Jun-07 15:25:01 UTC
There's nothing hi-res I'm afraid. The R520 review here has a die shot, I believe. Not available right now. Xenos die shot is out there somewhere, can't think where. Mostly I have these things on disk, not URLs (as the latter have a habit of disappearing)... Jawed

Posted by BrynS on Thursday, 07-Jun-07 16:50:20 UTC
Apologies for continuing the OT, but P.29 from the Stanford presentation:
Quoting ATI Radeon HD 2000 Series Architecture Overview by Eric Demers
What comes next?[...]-Tons of tuning for current architecture![...]

Posted by nAo on Thursday, 07-Jun-07 16:59:09 UTC
Not really surprising, it holds for any new architecture

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