PCI-SIG set to draft PCI Express Gen3 by year end
Thursday 09th August 2007, 05:05:00 PM, written by Rys
The PCI Special Interest Group, which controls the PCI Express
specification, looks set to draft the 3.0 revision of the interconnect
by the end of 2007, for review process and refinement in 2008, with
devices and hosts appearing in 2009.
Talking to EETimes, Al Yanes, chairman of the SIG and an engineer at IBM, outlined plans for the spec to drop the current 8/10b encoding scheme for the bitstream in favour of a scrambling polynomial scheme with boundary packets. The new scheme allows for higher usable bandwidth at the same transmission rate, but requires more processing to be done at both ends of the link, requiring extra silicon at the device and the interface (usually on northbridge for graphics) level.
The new scheme has less overhead than 8/10b and lets the specification scale to a sensible transfer rate without overly stressing vendors who would have to build the silicon to support it, both at the host and the device level, which might concern GPU vendors first of all. Graphics is the traditional driver of PCI Express in the market place, with graphics boards introducing Gen1 and about to debut Gen2 in the very near future.
According to EETimes there's some resistance to a part of the spec which governs the effective error rate, which might hold back development of interconnects which interface with PCIe Gen3, but Mr. Yanes didn't discuss the concerns.
With a supposed transmission rate of 8GT/sec, we wonder whether Gen3 will be the first revision of PCI Express to see mass-market transceiver implementations built using silicon photonics.
Talking to EETimes, Al Yanes, chairman of the SIG and an engineer at IBM, outlined plans for the spec to drop the current 8/10b encoding scheme for the bitstream in favour of a scrambling polynomial scheme with boundary packets. The new scheme allows for higher usable bandwidth at the same transmission rate, but requires more processing to be done at both ends of the link, requiring extra silicon at the device and the interface (usually on northbridge for graphics) level.
The new scheme has less overhead than 8/10b and lets the specification scale to a sensible transfer rate without overly stressing vendors who would have to build the silicon to support it, both at the host and the device level, which might concern GPU vendors first of all. Graphics is the traditional driver of PCI Express in the market place, with graphics boards introducing Gen1 and about to debut Gen2 in the very near future.
According to EETimes there's some resistance to a part of the spec which governs the effective error rate, which might hold back development of interconnects which interface with PCIe Gen3, but Mr. Yanes didn't discuss the concerns.
With a supposed transmission rate of 8GT/sec, we wonder whether Gen3 will be the first revision of PCI Express to see mass-market transceiver implementations built using silicon photonics.
Tagging
b3d ± pci, express, gen3, 2009, encoder
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