TSMC 40nm: Confusion Ahoy!

Tuesday 25th March 2008, 06:48:00 PM, written by Arun

TSMC unveiled their 40nm process yesterday, and seem to have confused a bunch of people in the process. So let's try to quickly set the record straight and see how this ties in with our earlier reports (1 & 2) on TSMC's roadmap.

There are two 40nm process variants; 40LP and 40G. The latter is actually the exact same node that was previously, and inaccurately, referred to as 45GS; indeed, there will not be a 45nm general-purpose nose at TSMC. 40LP, on the other hand, is a direct shrink of 45LP which has already been used by Qualcomm and Altera.

SRAM density is 0.242µm² versus ~0.29µm² for 45LP and 0.499µm² for 65nm. Gate density is ~1.19x and 2.43x that of 45LP and 65LP respectively. Leakage is similar to 45LP and 65LP while dynamic power consumption is 15% lower than 45LP and performance is unchanged. Dynamic power and performance numbers compared to 65LP for either 45LP or 40LP were not disclosed.

Both 45nm and 40nm have always been on TSMC's roadmap, but the 45nm general-purpose node was cancelled (it likely didn't make sense to have 45G and 40G one quarter apart!) and it's very plausible that 40LP has gained more traction than initially forecast, resulting in more customers skipping 45LP. We still expect 45GS/40G GPUs in very late 2008 or early 2009. On the low-power side of things, we'd expect the first tape-outs in Q2 ; the density advantage is quite small (8.5% linear shrink vs 10% for 55nm) but the lower dynamic power consumption seems very attractive in the handheld market.

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tsmc ± 45nm, 40nm, 45GS, 45LP, 40G, 40LP

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