TSMC 40nm: Confusion Ahoy!

Tuesday 25th March 2008, 06:48:00 PM, written by Arun

TSMC unveiled their 40nm process yesterday, and seem to have confused a bunch of people in the process. So let's try to quickly set the record straight and see how this ties in with our earlier reports (1 & 2) on TSMC's roadmap.

There are two 40nm process variants; 40LP and 40G. The latter is actually the exact same node that was previously, and inaccurately, referred to as 45GS; indeed, there will not be a 45nm general-purpose nose at TSMC. 40LP, on the other hand, is a direct shrink of 45LP which has already been used by Qualcomm and Altera.

SRAM density is 0.242µm² versus ~0.29µm² for 45LP and 0.499µm² for 65nm. Gate density is ~1.19x and 2.43x that of 45LP and 65LP respectively. Leakage is similar to 45LP and 65LP while dynamic power consumption is 15% lower than 45LP and performance is unchanged. Dynamic power and performance numbers compared to 65LP for either 45LP or 40LP were not disclosed.

Both 45nm and 40nm have always been on TSMC's roadmap, but the 45nm general-purpose node was cancelled (it likely didn't make sense to have 45G and 40G one quarter apart!) and it's very plausible that 40LP has gained more traction than initially forecast, resulting in more customers skipping 45LP. We still expect 45GS/40G GPUs in very late 2008 or early 2009. On the low-power side of things, we'd expect the first tape-outs in Q2 ; the density advantage is quite small (8.5% linear shrink vs 10% for 55nm) but the lower dynamic power consumption seems very attractive in the handheld market.

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Tagging

tsmc ± 45nm, 40nm, 45GS, 45LP, 40G, 40LP


Latest Thread Comments (6 total)
Posted by Time on Friday, 28-Mar-08 22:46:35 UTC
Maybe a stupid question but what's a half node (also referred to as an optical shrink)?

Posted by silent_guy on Saturday, 29-Mar-08 03:50:14 UTC
Quoting Time
Maybe a stupid question but what's a half node (also referred to as an optical shrink)?
It's a technology process that retains enough (almost all) characteristics of its parent node, so that you can use the same libraries, wire load models, etc., but that is smaller in size than the parent node. Since most of the characteristics are the same, a fab can roll out half-nodes much quicker than full nodes.Basically, you design, synthesize and do the place and route of the chip as if you're designing for the parent node, deliver the layout to the fab, which then optically reduces the layout to the smaller half node. Half nodes are usually slightly faster, since signal travelling distances are a bit shorter, but electrically, the transistors are usually hardly if any faster than the parent node.It's usually not possible to take an original, working, major node design and shrink it to its half node: analog cells often behave differently and certain digital characteristics may change enough to make them non-functional (slightly faster operation may result in hold time violations.) For analog cells, a common practice is to take the full node design, increase its size with the same amount it will be shrunk later on. The end result is an analog cell that's as big in the half node as it is in the full node and that behaves pretty much identical.

Posted by Time on Saturday, 29-Mar-08 04:32:01 UTC
Thank you, a perfect answer. (sorry for sounding like I'm scoring you)

Posted by Berek on Monday, 31-Mar-08 07:02:57 UTC
This should be an excellent step to the small form factor market; phones, MP3 players, and other handheld type of devices.It's interesting that they are skipping 45 GP? ATI and Nvidia are "almost" doing that with their video card series, although its a bit different in that they are essentially recycling the same technology into their current product lines, with the new "55nm" architectures coming out this summer.I'd like to see the power requirements of these... too bad this article didn't state any numbers this time around.

Posted by Arun on Monday, 31-Mar-08 11:48:48 UTC
Quoting Berek-Halfhand
This should be an excellent step to the small form factor market; phones, MP3 players, and other handheld type of devices.
Just making sure, you mean *for* the small form factor market, right? :) Since obviously process technology alone won't magically transform a design into something you can sell into handhelds.

Quote
It's interesting that they are skipping 45 GP? ATI and Nvidia are "almost" doing that with their video card series, although its a bit different in that they are essentially recycling the same technology into their current product lines, with the new "55nm" architectures coming out this summer.
I'm not sure what TSMC's process technology has to do with recycling GPU architectures - am I missing something here?

Quote
I'd like to see the power requirements of these... too bad this article didn't state any numbers this time around.
Yeah well if it's not supplied I can't make up numbers just to make people happy sadly! ;)

Posted by Berek on Tuesday, 01-Apr-08 07:16:41 UTC
Yes, you would be correct, sorry I forgot to add that word in there ;).As for the architectures, I'm just pointing out the parallels, not the similarities in technology itself.


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