It might have felt as if VIA’s CPU designers were sleeping for the last 3 years and asked the package and PCB engineers to keep the company going for the next thousand years. But today, they prove nothing could be further away from the truth.

VIA’s Isaiah (aka CN) was designed by the same Centaur Technology team that developed all their previous processors, but it is by far the most disruptive change in architecture in the company’s history. The complexity of the architecture takes a huge jump, from the single-issue 486-like C7 to something that in many ways resembles Penryn more than any other chip out there. It sports out-of-order execution, x86-64, and a sophisticated microarchitecture.

That doesn’t mean it’ll attain similar IPC (it won’t), but it won’t compete in the same markets either according to our own analysis:

  • Isaiah ULV: Slowest SKU @ 3.5W, presumably 1GHz (?). To be compared against Core 2 Solo ULV @ 5W running at 1067MHz and 1200MHz and against Silverthorne @ 2W running at up to 1.86GHz.
  • Likely to be at a performance/watt advantage against the 65nm Core 2 Solos but at a disadvantage against Silverthorne due in great part to Intel’s 45nm process superiority.
  • Isaiah Embedded: Unknown TDP (5-25W?) and will compete against AMD’s 65nm Sempron @ 8W running at 1GHz and Intel’s diverse embedded solutions.
  • However, VIA might also have the advantage of using a low-power single-chip chipset against both Core 2 Solos and embedded products from AMD/Intel.
  • Isaiah Desktop: Top TDP of 25W (?) @ 2GHz, unknown minimum TDP (5 or 7W?) – will compete against low-end AMD Semprons and Intel’s Conroe-based Single-Core Celerons, and also fit in a niche below that. Substantially lower TDPs.

VIA released an Architecture Brief written by Glenn Henry, President of Centaur Technology (and lead engineer/only manager), on Isaiah’s architectural details. Pretty much every single bit of architecture information available from all the articles on the web are in there (and I should know, I practically read them all!) so it’s certainly worth a good read in our opinion if you’re comfortable with that kind of presentation and detail. There also are both Isaiah and C7 die shots on several websites, which should be easy to Google for if you want to.

An interesting point to consider is that, unlike C7 which was an incredibly small and cheap chip for its time (30mm²), the 65nm Isaiah (60mm²) is actually not much smaller than Intel and AMD’s competing chips (and it is much larger than Silverthorne). Centaur seems to have two excuses for that: first of all, they decided to optimize the design for power efficiency more than area efficiency (source: Secondly, the L2 cache does take a much larger share of the die than on C7 (but not that much more than on a 65nm Sempron).

There are several other factors and misc. tidbits also worth mentioning. For example, The Tech Report and The Inquirer are implying the foundry is none other than… Fujitsu! It does make some sense given that VIA/S3’s latest GPUs have been manufactured there. Also, it is likely that the wafer cost is lower than for C7 (which was at IBM on 90nm SOI; Fujitsu uses bulk silicon) but it’s not obvious by how much.

Regarding the package, initial samples are 21x21mm but VIA has promised to also deliver a 11x11mm package in the future. Both are similar to C7's and fully socket-compatible. Finally, our interpretation of TSMC’s official claims and various rumours is that Centaur is likely to switch to TSMC’s 45nm high-performance process in 2009 for Isaiah (with 40nm-like density as we reported previously), possibly high-k/metal gates if TSMC delivers that process variation on time (which seems unlikely at this point, sadly).