Intel reveal Penryn and Nehalem details to press
Thursday 29th March 2007, 07:07:00 PM, written by Rys
Intel, in a conference call with various members of the online technology press, have revealed some key details about their upcoming 45nm processor families. Penryn encompasses the evolution of the Core architecture on Intel's latest production process, while Nehalem is brand new, taking things to some new levels for the chip giant.
Intel's 45nm process
Before the Penryn and Nehalem chatter, it's worth a quick recap on what that process brings to the table for microprocessor production for those that haven't seen PodTech's video coverage or similar written coverage that came when Intel talked about 45nm back in January.
Effectively, the advancements Intel have rolled out with their 45nm process technology, center around the use of a high-k dielectric for the transistor's gate insulator, and the use of a metal for the gate itself rather than a polysilicon. The materials changes in the transistor itself let it leak less idle power, take less power to switch, and switch faster. So Intel build their 45nm transistors using fundamentally different materials than before at 65 and higher, such that Kelin Kuhn probably deserves a pay rise right about now, given how bullish Intel are about how 45 is going to help their processor production efforts in the next couple of years.
Penryn
Penryn is the name for the migration of the Core architecture that debuted on 65nm, to the 45nm process outlined above. The migration encompasses an evolution for the basic hardware, too, rather than just a simple port to 45 with nothing changed. Penryn family processors still retain their basic dual-core setup, with quad-core a pairing of dice on one package, but they get a few new additions to help performance in a number of areas.
Shared L2 per die jumps to 6MiB for the top-end product, accounting for much of the transistor count increase Penryn family processor will have versus their 65nm Conroe and Kentsfield counterparts. SSE4 also makes an appearance, that x86 ISA extension centered on improving data alignment ops with 50 new instructions. Intel are also introducing a new division unit, optimised for both FP and integer division and able to work on 4 bits per clock, versus 2 in 65nm Core processors. Software rasterisers should go usefully faster on Penryn-family processors, then.
Further highlights include better deep sleep power management, 1600MHz bus clocks (although maybe just for Xeon), confirmed clock speeds of over 3GHz (likely 3.46GHz on a 1066MHz bus, 3.6GHz for 1600MHz) for the top end models and no more than 65W TDP for dual-core models (130W for quad-core, somewhat predictably). HEXUS have a good summary of the goodies.
Nehalem
Nehalem, named after a river and bay in Oregon, was the clear highlight of Intel's conference call however. It's on 45nm of course, and contains the aforementioned SSE4 x86 ISA extension, that much should be obvious without having Intel's Stephen Smith whispering in your ear.
Nehalem-family processors will also stick with an evolution of Core in terms of instruction issuing too, retaining Core's ability to retire 4 instructions per clock cycle.
What possibly wasn't expected was the introduction of an on-die DDR3 memory controller, on-package IGP, the return of an SMT processor front-end, point-to-point system interconnects for Nehalem processors and its supporting core logic and new cache management schemes to help threads get the most of out the multi-level (L3?) cache system Nehalem will employ.
Intel mention 16 threads in a socket for Nehalem, indicating two quad-core dice with their SMT scheme active. The integrated memory controller and point-to-point interconnect, apeing what Opteron brought to the table with its MC and HyperTransport, should help in an overall available system bandwidth sense, both at the physical memory level and between components in a Nehalem system that communicate using the new interconnect.
In terms of the integrated IGP however, and the technology that's likely to employ, we'll discuss that in another piece. It's not too much of a stretch to imagine SM4.0 graphics technology next to the CPU dice in the same socket, with volume shipments for Nehalem starting in H2 next year. However it remains to be seen whether that includes integrated IGP SKUs or not, with that almost complete system-on-package approach, in one socket.
HEXUS have good coverage of Nehalem's basic points, and we'll follow up on the IGP chatter in due course.
Tagging
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