Intel talks Itanium's architecture refreshes and road map up-to 32nm
Tuesday 19th June 2007, 09:09:00 PM, written by Farid
Intel’s only high-end CPU entirely based on a RISC architecture CPU, targeted toward servers, Itanium, was the centre of the talk Diane Bryant –Vice President and general manager for Intel's Server Platforms Group- had with reporters during a press conference held at San Francisco, last week, reports EE Times.
Intel considers the dual-core Montvale, which will replace the current Itanium 2 (Montecito), to be on track for a release later this year on a 90nm process, but declined to be more specific about a date.
The 2008 plans for Itanium take form as Tukwila, a 65nm quad-core processor. It will be based on the same architecture as Montecito and Montvale but will support some refinements, such as a more threads per core, leading to a higher IPC, a new high-speed front side bus and integrated memory controllers, supporting the "double device data correction" technology, which can handle DRAM errors on two discrete modules. Interestingly, the CPU will share a common chipset with the other Intel’s high-end family of chips, Xeon. A move that should please AIBs’ inventory management, we’re sure.
The real big architectural change in the Itanium line will be introduced after 2008 with the chip codenamed Poulson. The CPU is still kept under wraps by Intel but the company let know that it would be fabricated on a 32nm process, have more than 4 cores and support more threads per cores. While Intel considers Poulson as a major architecture overhaul, it made clear that the chip will be perfectly compatible software developed on older Itanium platforms.
Intel considers the dual-core Montvale, which will replace the current Itanium 2 (Montecito), to be on track for a release later this year on a 90nm process, but declined to be more specific about a date.
The 2008 plans for Itanium take form as Tukwila, a 65nm quad-core processor. It will be based on the same architecture as Montecito and Montvale but will support some refinements, such as a more threads per core, leading to a higher IPC, a new high-speed front side bus and integrated memory controllers, supporting the "double device data correction" technology, which can handle DRAM errors on two discrete modules. Interestingly, the CPU will share a common chipset with the other Intel’s high-end family of chips, Xeon. A move that should please AIBs’ inventory management, we’re sure.
The real big architectural change in the Itanium line will be introduced after 2008 with the chip codenamed Poulson. The CPU is still kept under wraps by Intel but the company let know that it would be fabricated on a 32nm process, have more than 4 cores and support more threads per cores. While Intel considers Poulson as a major architecture overhaul, it made clear that the chip will be perfectly compatible software developed on older Itanium platforms.
Tagging
intel ± itanium, montecito, montvale, poulson
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