IBM presents 45nm Cell B.E. at ISSCC

Thursday 07th February 2008, 10:10:00 PM, written by Carl Bender

IBM introduced the 45nm version of the Cell B.E. processor at ISSCC earlier this week, fabbed on IBM's 45nm SOI line at East Fishkill and targeted primarily towards future revisions of the Playstation 3 gaming console and Cell blade servers. Notable among the achievements in the process transition is a greatly improved power profile, which has come down 38% in TDP relative to the 65nm shrink, and by over half compared to the original 90nm version of the chip. If previously revealed figures for the 90nm Cell are an indication, this would put the 45nm Cell at under 50 watts peak power draw at an operational frequency of 3.2GHz. Key in achieving these gains was the introduction of an independent SRAM voltage supply in the previous 65nm shrink, which has allowed core voltage to be lowered while maintaining stability and high operational frequencies in the L2 cache and SPE local stores. With the 45nm shrink, core voltage has been reduced to 0.8v from 0.9v for the 65nm processor.

The increased efficiency has allowed for significant gains in clockspeed as well, with stable operation at 4GHz registering below the power demands required of the 65nm Cell@3.2GHz, and speeds of 6GHz reached using a voltage of 1.15v. Although such chips will clearly not see use within Sony's console, the option would be open to IBM and/or Mercury to ship updated hardware taking advantage of the much improved Flop/watt ratio. The PS3 should benefit, however, from the associated reduction of cooling and power supply overhead; areas that have already seen initial cost reductions in the 40GB with the introduction of the 65nm Cell.

Less exciting than the thermal and frequency gains has been the pace of die size reduction, which after the second full node shrink has only now come down to an area of ~115mm2, a size that would not have seemed out of place had it been reached on the previous 65nm node (the original 90nm chip had a die area of 235mm2, and the 65nm chip an area of ~174mm2). Plaguing the rate of reduction are the analog circuits and I/O logic associated with the Rambus interfaces, which place a higher cap on the dimensional reduction of the die than could otherwise be achieved. Having gone through an automated scaling process in order to reduce costs associated with heavy optimization, the 45nm Cell now features small bands of 'dead' silicon to the north/south of the chip topography, bordering the SPE arrays - a reflection of the constraints faced in reducing the dimensions of the FlexIO and XDR interfaces located on either end of the processor.

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