Further Intel Penryn details emerge
Saturday 27th January 2007, 12:12:00 PM, written by Arun
Dailytech and Hexus
both have a bunch of new mini-facts on Penryn today, among which what
they claim is the first official die shot of 'Penryn'. Apparently, most
of the extra transistors (410M vs 298M for Conroe) will be used for
extra cache (6MiB vs 4MiB), although the chip also implements SSE4 -
but it is unclear to us whether most of these are actually new native
instructions or not.
Given how much of incremental improvement Penryn seems to be, it wouldn't be too surprising if this was mostly a way to improve the addressable market of SSE4, while the biggest boosts from these instructions would be for Intel's upcoming Nehalem microarchitecture. At the same time, Intel's CEO recently said in a conference call that Penryn would get specific performance boosts for floating point code. Given that K8L is said to have substantially improved FP64 performance and SSE performance hopefully matching that of Conroe, it would be quite interesting if Intel decided to further boost their FP units, in addition to adding these new SSE4 instructions.
At this point, nobody really seems to know what Intel actualy did (if anything!) for FP with Penryn - but this will surely have a significant impact on Intel and AMD's respective competitiveness in the server market. Furthermore, Intel is marketing high-k and metal gates extensively for the 45nm transition, and righly so - it's likely to be one hell of a nice boost to performance/watt. Even with SOI, AMD is very unlikely to match Intel's 45nm leakage levels for some time, so it will also be interesting to watch how much that affects the bigger picture, and whether AMD can remain competitive in the notebook space anyway - at least until they catch up with 45nm high-k metal gates in 2008, as announced today by IBM. TSMC, on the other hand, is not planning to introduce high-k metal gates before the 32nm process node.
Given how much of incremental improvement Penryn seems to be, it wouldn't be too surprising if this was mostly a way to improve the addressable market of SSE4, while the biggest boosts from these instructions would be for Intel's upcoming Nehalem microarchitecture. At the same time, Intel's CEO recently said in a conference call that Penryn would get specific performance boosts for floating point code. Given that K8L is said to have substantially improved FP64 performance and SSE performance hopefully matching that of Conroe, it would be quite interesting if Intel decided to further boost their FP units, in addition to adding these new SSE4 instructions.
At this point, nobody really seems to know what Intel actualy did (if anything!) for FP with Penryn - but this will surely have a significant impact on Intel and AMD's respective competitiveness in the server market. Furthermore, Intel is marketing high-k and metal gates extensively for the 45nm transition, and righly so - it's likely to be one hell of a nice boost to performance/watt. Even with SOI, AMD is very unlikely to match Intel's 45nm leakage levels for some time, so it will also be interesting to watch how much that affects the bigger picture, and whether AMD can remain competitive in the notebook space anyway - at least until they catch up with 45nm high-k metal gates in 2008, as announced today by IBM. TSMC, on the other hand, is not planning to introduce high-k metal gates before the 32nm process node.
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