Intel Terascale: 3GHz, Scalar & VLIW
Monday 12th February 2007, 12:12:00 PM, written by Arun
While Larrabee is likely what many graphics enthusiasts and engineers
are pondering upon right now, it is hardly the only FP-rich project
going on at Intel. Further details have emerged today on Intel's
Terascale chips, also known as Polaris. Anandtech has a full article on the subject, and it certainly puts the project in another perspective.
Polaris has 80 cores, but what wasn't known previously is that it reaches a teraflop of floating-point performance without vector units, but rather with high clock speeds (3.2GHz+) and two scalar FMACs (multiply and accumulate) per core. Instruction scheduling and decoding overhead is also kept minimal through a VLIW (Very Long Instruction Word) architecture. Furthermore, the chip is merely 275mm2 on 65nm, at 98W at 3.2GHz, or 11W at 1GHz. Right now, tiles only contain FMACs, but you'd expect that to change in future architecture iterations. The chip is also fundamentally 80 times the same 3mm2 tiles, which implies that it most likely is fully custom logic.
The big question now is, in 5 years' time, is this a worthy GPGPU competitor; or possibly even an architecture capable of making the GPGPU paradigm fundamentally obsolete? It certainly has some amazing potential, but the design choices have nothing to do with those of current GPUs, which makes it hard to properly estimate. For example, the branching characteristics would be completely different.
The most surprising aspect, perhaps, is that the architecture seems to be latency-intolerant, but is coupled with stacked memory to minimize that problem and simulatenously maximize bandwidth. This is a fundamentally different paradigm from today's latency-tolerant GPUs. As such, much of the potential of Polaris as a concept has yet to be known, as it depends greatly upon the performance and size of its stacked memory, and of the overall architecture's latency, bandwidth and caching characteristics.
Polaris has 80 cores, but what wasn't known previously is that it reaches a teraflop of floating-point performance without vector units, but rather with high clock speeds (3.2GHz+) and two scalar FMACs (multiply and accumulate) per core. Instruction scheduling and decoding overhead is also kept minimal through a VLIW (Very Long Instruction Word) architecture. Furthermore, the chip is merely 275mm2 on 65nm, at 98W at 3.2GHz, or 11W at 1GHz. Right now, tiles only contain FMACs, but you'd expect that to change in future architecture iterations. The chip is also fundamentally 80 times the same 3mm2 tiles, which implies that it most likely is fully custom logic.
The big question now is, in 5 years' time, is this a worthy GPGPU competitor; or possibly even an architecture capable of making the GPGPU paradigm fundamentally obsolete? It certainly has some amazing potential, but the design choices have nothing to do with those of current GPUs, which makes it hard to properly estimate. For example, the branching characteristics would be completely different.
The most surprising aspect, perhaps, is that the architecture seems to be latency-intolerant, but is coupled with stacked memory to minimize that problem and simulatenously maximize bandwidth. This is a fundamentally different paradigm from today's latency-tolerant GPUs. As such, much of the potential of Polaris as a concept has yet to be known, as it depends greatly upon the performance and size of its stacked memory, and of the overall architecture's latency, bandwidth and caching characteristics.
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