The R520 Graphics Chip

Here is a quick overview of the R520 chip details and a summation of the capabilities.

Chip Details
Chip Name R520
Silicon Process 90nm (TSMC)
Transistors 321M
Die Size 288mm²
[16mm (w) x 18mm (h)]
Packaging Flipchip
Pipeline Configuration 16 / 16 / 16
(Textures / Pixels / Z Samples per clock)
Memory Interface 256-bit (32x8 Crossbar)
GDDR1 to GDDR4
DirectX Capability DX9.0 - VS3.0, PS3.0
Display Dual 400MHz RAMDAC, Dual Dual-DVI, Xilleon TV Out
Host Interface PCI Express x16



R520 ChipR520 Die

The package for R520 is one of the largest seen so far for a graphics processor and this is largely due to the number of grounding pins required, given the voltages it can run at.

Taking a closer look at the shot of the die functional blocks can clearly be seen, including the four quad pixel processing pipelines. What is surprising is the size of the large block close to the centre (just to the left); we are told that this area of die actually relates to the memory controller, which looks like it has been given a fairly large die area.

With the use of the 90nm process R520 can make use of Dynamic Voltage Control. Dynamic Voltage Control can allow software control over the voltage supplied to the chip in order to scale down the performance under scenarios it is not needed, such as 2D operation, and then scale them back up when higher workload demands are placed on it, such as rendering complex 3D scenes.

Here is an overview of the features made available by the R520 chip:

  • Ultra Threaded Shader Engine
    • Support of DirectX9 Programmable Vertex and Pixel Shaders
    • VS3.0 Vertex Shader functionality
      • 1024 Instructions (Unlimited with flow control)
      • Single Cycle Trigonometric Operations (SIN & COS)
    • PS3.0 Pixel Shaders
      • Ultra Thread Pixel Shader Engine
      • Fast Dynamic Branching
      • Single Precision 128-bit Floating Point (FP32) Processing
      • 16 textures per rendering pass
      • 32 temporary and constant registers per pixel
      • Facing register for two-sided lighting
      • Multiple render target support
      • Shadow volume rendering acceleration
      • 128-bit, 64-bit & 32-bit per pixel floating point colour formats
  • Advanced Image Quality Features
    • HDR Blending on FP16, Int10 and Custom Formats
      • All Blending modes work with all Anti-Aliasing Modes
    • 3Dc+ Normal Map Compression
      • High quality 4:1 Normal Map Compression
      • Two Channel & Single Channel format support
    • 2x/4x/6x Multi-Sampling full scene Anti-Aliasing modes, adaptive algorithm with programmable sample patterns and colour buffer compression
    • Adaptive Anti-Aliasing for Transparent Surfaces
    • Temporal Anti-Aliasing
    • Lossless Color Compression (up to 6:1) at all resolutions, including widescreen HDTV resolutions
    • High Quality, Angle Invariant, Anisotropic Filter Mode
    • 2x/4x/8x/16x Anisotropic Filtering modes
    • 4Kx4X texture Support
  • Ring Bus Memory Controller
    • Internal Ring Bus Architecture
    • Programmable Arbitration Logic
    • Fully Associative Caches
    • 3-level, Floating Point, Hierarchical Z-Buffer with early Z test
    • Lossless Z-Buffer compression (up to 48:1)
    • Fast Z-Buffer Clear
    • Z Cache Optimisations for shadow rendering
    • Optimized for performance at high display resolutions, including widescreen HDTV resolutions
  • AVIVO
    • Dual 10-bit Display Pipelines
    • Dual Integrated Dual Link TMDS Transmitters, Dual 400MHz RAMDACS, Xilleon Derived TV Output.
    • Hardware Accelerated H.264 Decode

As the specification rundown indicates R520 has support for ATI's AVIVO technologies, and fully supports all of the video decode to display elements outlined in our article here.