AMD announces SSE5 instructions

Thursday 30th August 2007, 06:12:00 AM, written by Tim

AMD today announced a new extension of the SSE SIMD instruction set in the form of SSE5, a fairly radical upgrade that will arrive in 2009 with the "Bulldozer" core. The full instruction set reference is here, and we've also got a quick overview of new features:
  • There are now instructions that take three arguments in addition to the destination. As a result, there are new instructions that multiply two registers and add a third (much like most ALUs on a GPU) .
  • FP16, everyone's favorite partial precision format from the NV30 era, is back. All of the instructions for the new FP16 format are related to the new multiply-accumulate class of instructions.
  • There are a number of new instructions to move values within an XMM register. There's a new instruction, PPERM, to generate permutations of the contents of an XMM register, as well as vector rotates, shifts, and conditional moves.
It's fair to call this a new version of SSE as opposed to 3DNow, AMD's previous SIMD instruction set, since it uses the XMM registers introduced with SSE. Of course, there's the question of whether or not Intel will support it, or for that matter whether AMD will fully support SSE4. Barcelona supports SSE4a, a subset of SSE4, plus the extra POPCNT instruction, but there's no mention of whether Bulldozer will support SSE4 completely. If we had to guess, though, we'd say that Bulldozer will skip the rest of SSE4 completely. SSE5 defines a number of rounding instructions (ROUNDPS, ROUNDPD, etc) that were already present in SSE4.

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