Fabtech blog posts: Foundries' Squeeze + Memory

Saturday 09th February 2008, 12:20:00 PM, written by Arun

Mark Osborne at Fabtech.org posted two interesting blog posts in the last couple of days, one on the apparent capacity expansion squeeze from foundries in an attempt to improve wafer prices and margins, and another on the current (awful) state of the memory markets. They're both definitely worth a read if you're interested in that kind of thing.

Here are the key points in the foundry-related post:

• Wafer prices have dropped ~19% between 2004 and 2007 industry-wide.
• TSMC, UMC and Chartered's drops were 19%, 28%, and 11% respectively.
• UMC's wafer pricing is currently 20% lower than TSMC's on average, but the process mix is likely different so it isn't fully comparable. Chartered and SMIC are priced even lower.
• TSMC has been the only company with significant 300mm fab expansion over the last 5 years, and getting customers to migrate away from 200mm has been very challenging.
• Capital Expenditure from all foundries in 2008 will be lower than in 2007 according to public financial guidance.
• Mark proposes several explanations to this, including the desire to get customers to migrate to 300mm by increasing wafer ASP and limiting 200mm capacity.
• Leading-edge process utilization is very high, but Mark judiciously points out this figure only counts utilised tools, and not available tools already installed or extra cleanroom space.
• The foundries' public strategy is clearly to stop the wafer price erosion though, as they claim ti has been faster than their cost reductions in recent years. TSMC, at least, claims to be confident in being able to do so.

There are two interesting points I'd like to point out myself, at least in the case of TSMC: first of all, wafer pricing for the first half of 2008 has been decided with customers some time ago. And secondly, capital expenditure in 2008 is front-loaded, with the second half forecasted as being substantially leaner than the first in terms of capital expenditure.

This implies that in general, the effects of this 'squeeze' likely won't begin until very late 2008. And if capacity really becomes too tight, foundries likely still have a few tools in reserve to meet demand - but at high utilisation rates and lead times, nonetheless. Beyond that, another key question is the strategy for 45nm. We'd certainly expect foundries to fight as hard as they can to keep a wafer price premium there.

Discuss on the forums

cpu ± foundry, tsmc, umc, chartered, smic

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