[Analysis] TSMC 40G to deliver up to 3.76x the perf/mm^2 of 65G & Power Implications

Thursday 01st May 2008, 09:27:00 AM, written by Arun

It turns out TSMC's 40nm general-purpose process will be even more impressive than previously expected: we knew it was going to sport 2.35x the gate density of 65nm, but now it turns out it'll deliver 60% higher performance too for a theoretical 3.76x perf/mm² boost. But power improved much less.

TSMC's 55nm process improves power efficiency by up to ~10%, but performance remains unchanged; so that's a 1.23x perf/mm² improvement over 65nm. The latter was a 30-50% performance improvement over 90nm (and a bit less over 80nm), while also sporting ~2x 90nm's gate density. Similarly, 90nm was a 30-35% performance improvement over 130nm and it achieved ~2x 130nm's gate density.

So clearly the 40nm step will be a bigger step than usual. It's worth pointing out, however, that SRAM scaling from 65/55 to 45/40 is less impressive than gate density; it's only ~2x. That's a pretty sharp contrast to the 130->90nm transition, which was the exact opposite: ~2.45x the SRAM density and ~2x the gate density! It is unclear if this is mostly for technical reasons, or if customer focus on logic-rich chips had something to do with it.

Generally speaking, TSMC's gate density and performance figures often seem slightly overoptimistic, however they remain fairly accurate and aren't massive exaggerations, so this is certainly good news for TSMC's customers including NVIDIA and AMD. However, there's a catch: even if practical perf/mm² might improve by more than 3x over 65nm, power-per-transistor won't magically go down 67%. So if you thought perf/watt was important in the last few years, you haven't seen anything yet.

From an economic perspective, this also has very severe implications on NVIDIA and AMD's strategy and what constitutes the 'perf/mm² vs perf/watt' sweetspot. The problem is simple: if you double both performance and wattage for a given chip cost, your PCB and cooler costs go up. If that happens, your overall Bill of Material (BoM) for the final end-consumer product goes up. And that means the relative chip costs go down for a given retail price tag; so assuming the end-consumer market doesn't grow, the amount of money that goes to TSMC goes down - and assuming constant gross margins for NVIDIA and AMD, their revenue and profits also go down.

This is obviously a major problem and we predict that in the coming years, executives and the investment community will slowly realize that gross margins are an outdated concept for semiconductor companies; while they do matter, they shouldn't be the real focus. The real focus should be 'gross margins * percentage of BoM' because it turns out there are a lot of strategic dynamics that can affect the latter by a significant amount in the coming years. This is both true at the board level and the overall system level.

Those who take the naive approach and focus on gross margins exclusively, rather than how much gross profit they can extract out of a final BoM, are destined to fail horribly. This is why chip design & synthesis will be more and more about perf/watt rather than perf/mm², because it turns out the most perf/mm²-efficient design might actually result in lower gross profits for your company. Similarly, other more exotic ideas including embedded memory might prosper in certain segments of the market in such an environment, while the cost-efficiency of others (such as multi-chip designs) might become much more complex to estimate.

And it's not just about cost efficiency; it's also about thermal limits and the implications on the ultra-high-end. We're already very near those thermal limits today, so if perf/mm² grows much faster than perf/watt and cost-per-mm² doesn't grow too much either, then we risk being completely limited by thermals in the $500+ market. And don't kid yourself: there's no evidence of 32nm or high-k magically fixing this either. Once again, the only real solution is to emphasize perf/watt throughout the design and synthesis process at the expense of perf/mm². Both dynamic power and leakage are important, although obviously the former remains the predominant issue.

In related news, it looks like TSMC's plans for 32nm and high-k changed a bit in the last few months: it was previously indicated that that there would be a 40nm variant with high-k, and that the first 32nm variant would be low-power for handhelds. And now it turns out only 32nm will have a high-performance variant with high-k (aimed at the CPU market) and the first 32nm variant will be... general-purpose, which means usable for PC GPUs. This is in sharp contrast to the 90nm and 65nm nodes, where the low-power variant came significantly earlier than the general-purpose one. 32G risk production is slated for 4Q09, and 32LP is slated for 1Q10.

Why this sudden change? Likely two things: first, Larrabee. NVIDIA is TSMC's largest customer right now, and AMD is also amongst the the largest ones. So if they want TSMC to prioritize their 32G process to improve their chances against Intel, they've got a lot of weight to make that happen. Secondly, the power benefit from 40nm to 32nm when considering both dynamic power and leakage may not be so impressive, and many handheld SoC manufacturers are moving to single-chip solutions that integrate some RF and analogue. In that context, wafer prices and yields are likely more important than gate density improvements.

In conclusion, TSMC looks like they're delivering very well on their roadmap and getting ahead of everyone else in the industry, at the obvious exception of Intel. That doesn't allow them, however, to break the laws of physics; silicon still leaks, and power density is still going up. Both will have increasingly important effects on the semiconductor industry, and executive-level strategic decisions must be made with proper consideration of the severe changes ahead.

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